Anti-fuse structures have been used in the semiconductor industry for memory related applications, such as, for example, field programmable gate arrays and programmable read-only memories. Prior art anti-fuse structures typically include a material which initially has a high resistance, but can be converted into a lower resistance material upon application of certain processes. For example, an unprogrammable anti-fuse type gate array can be programmed by causing selective anti-fuses to become conductive.
FIG. 1 is a cross-sectional representation of a prior art anti-fuse structure which includes a first metal layer 14, an anti-fuse layer 16, and a second metal layer (e.g., interconnect layer) 22 embedded in a dielectric layer 18. During programming, an appropriate voltage between the first metal layer 14 and the second metal layer 22 is applied and that applied voltage creates a conductive path. That is, the applied voltage lowers the electrical resistance of the anti-fuse structure.
The process for integrating the prior art anti-fuse structure mentioned above requires many extra masking and etching steps, which increase the overall fabrication cost. Also, since the programmable voltage for creating the electrical path is a function of the thickness of the anti-fuse layer 16, the anti-fuse material damage, which is a result from a dielectric over-etch, can cause deprogrammed states and result in product failure, i.e., the electrical path is not properly formed when an appropriate voltage is applied. Moreover, the voltage programming method requires a sandwich structure with a layer of anti-fuse material between two ‘disconnected’ conductive materials. This requirement of the prior art structure illustrated in FIG. 1 limits the design flexibility and enlarges the area required for forming an element.
Some variations to the basic anti-fuse structure defined hereinabove can be found in the following literature:
U.S. Pat. No. 5,789,795 to Sanchez, et al. entitled “Method and apparatus for fabricating anti-fuse devices” disclose an etch layer disposed above the anti-fuse material, and an inter-metal oxide layer disposed above the etch layer. The inter-metal oxide has a via formed therein.
U.S. Pat. No. 6,335,228 to Fuller, et al. entitled “Method for making an anti-fuse” provide a process for producing dynamic random access memory (DRAM) having redundant components including steps for concurrently forming normal contacts and anti-fused contacts.
U.S. Pat. No. 6,251,710 to Radens, et al. entitled “Method of making a dual damascene anti-fuse with via before wire” disclose an anti-fuse structure which includes a substrate having a first level of electrically conductive features, a patterned anti-fuse material, a patterned interlevel dielectric material and a second level of electrically conductive features.
U.S. Pat. No. 6,124,194 to Sanchez, et al. entitled “Methods of fabrication of anti-fuse integrated with dual damascene” provide an anti-fuse process which uses a SiN layer to pattern at least openings. First openings expose the metal via and second openings expose a portion of the first dielectric that is above the second metal line.